The present invention pertains to computing systems, and more particularly to a store buffer apparatus in an improved, high performance, multiprocessor or uniprocessor computer system.
In the design and development of computer systems, increasing emphasis is being placed on performance of such systems. The performance is very often a function of the technology used in manufacturing the integrated circuit chips which comprise the computer system. One such technology, new in the development of computer systems, is Complementary Metal Oxide Semiconductor (CMOS) technology. CMOS technology provides a greater degree of reliability, serviceability, and availability than seen before in prior computer systems, due mostly to a reduction in the physical number of chips which comprise the computer system. Since a scarcity of input/output pins on chips has been a problem with prior computer systems, a reduction in the number of chips reduces the number of interconnections (input/output pins) between chips In addition, performance may also be a function of the number of processors which comprise the computer system.
In such processors, master storage facilities store data needed by the central processor units (CPU). In a multiprocessor system, each processor often included a small cache memory in addition to the master storage facilities. The cache was used by a particular processor to store blocks of instructions or data. If the data or instructions were needed by the processor, a particular item of data or an instruction was retrieved from the cache in lieu of the master storage facility, since the time required to perform a fetch from cache is much smaller than the time required to fetch from master storage. However, if a particular processor retrieved data and/or instructions from cache and executed the instructions and/or operated on such data yielding a set of results which required storage in the master storage facility, it is necessary that the particular processor store the set of results directly to the master storage, not via the cache. However, if a first CPU of the multiprocessor system is using the master storage facility, a second CPU cannot store the set of results in the master storage facility until the first CPU is finished using the facility.
In a uniprocessor mode, the master storage facility can also be tied up by the channel facilities. This way the processor itself can not store the result back into the master storage facility until the master storage is freed up by the channel facilities Thus the processor can not execute the next instruction until the channel facilities finish using the master storage facility. Therefore, the execution of another instruction in the second CPU is delayed until the master storage facility is freed up by the first CPU or by the channel facilities.
Furthermore in a pipeline machine, the processor has the capability to store results back into the master storage facility every machine cycle. Usually the rate of storing data into the master storage facility is much slower than the rate the processor generates the data to be stored away. Hence the processor has to stop executing instructions while the master storage facility is still busy storing the result for the current instruction. In other words, the master storage facility can not keep up with the processor.